1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to integrated circuit memories having sense amplifiers and timing circuitry for controlling activation of those sense amplifiers at a controlled time following a read request.
2. Description of the Prior Art
It is known to provide integrated circuit memories with sense amplifiers for detecting bit line voltage changes when reading data from an array of bit cells and subsequently interpreting the data. The sense amplifiers typically consume a relatively large amount of power and accordingly it is desirable not to switch them on until necessary (e.g. when suitable voltage levels for a fast sense amplifier flip speed are present) and then switch them off when they have done their work. However, given the variations in process, voltage and temperature variations, as well as other variations, that can impact the performance and operation of an integrated circuit, the precise timing of switching on and switching off the sense amplifiers needs to adjust to take account of these factors. To this end, it is known to provide self timing paths as part of the timing circuitry within such integrated circuits.
FIG. 1 illustrates a known type of self timing path. An integrated circuit 2 includes a memory system 4 as well as other circuit elements such as a microprocessor core 6. A read request is generated and passed to a timing controller 8. The timing controller 8 initiates a set signal on signal line 12 which is dimensioned and routed in a manner which models the memory's word line and which propagates to a number of pull down transistors 10 which serve to pull down the voltage on a signal line 13 which is dimensioned and routed in a manner seeking to model the bit lines running through an array of bit cells 14. The propagation delay along the signal (delay) lines 12 and 13 and the action of the pull down transistors 10 is selected such that the reset input to the timing controller 8 will be received after a delay period following the read request; the delay period is intended to correspond to the amount of time after which the address decoding, word line selection and bit line driving operations (as well as other necessary operations) will have been performed for the array of bit cells 14 such that the bit line signals will be available for reading by the sense amplifiers 16. Accordingly, the timing controller 8 will then activate the sense amplifiers and reset itself ready to receive the next read request.
A problem with the system of FIG. 1 is that, in order to achieve high density within the array of bit cells 14, these are often formed with their own process and performance parameters which are different from those used in the rest of the integrated circuit 2. This enables high density and low power consumption to be achieved within the array of bit cells 14. However, a consequence is that the behaviour of the pull down transistors 10 and the signal (delay) lines 12 and 13 will not sufficiently accurately model the behaviour of the array of bit cells throughout the full range of process, voltage and temperature variations. Additionally, resetting the timing circuit 8 before the sense amplifiers 16 adds in additional logic delay not found in the true bit cell read path. Accordingly, additional margining is added into the operation of the timing controller 8 which reduces overall performance. These problems are becoming more significant as the size of the process geometries reduces to 90 nm and below. Additionally, whereas in the past limitations associated with read operation were dominant in constraining performance, write operations are now becoming limiting in some process/voltage/temperature parameter corner cases. A single functional delay path built to account for both worst case read and worst case write performance would be disadvantageously limiting. An assumption that read and write can be handled in the same way and with the same timing is no longer true at these process sizes and below.